Many existing systems use a Peripheral Component Interconnect Express (PCIe or PCI-E) common clock architecture (CCA). PCIe is a serial bus standard for connecting a computer to one or more peripheral devices. Careful attention must be applied to control the clock skew at each point in the system. Conventional PCIe systems include constraints on connector pins, constraints on routing lengths, zero delay buffer (ZDB) constraints, especially with spread spectrum clocking (SSC), and transport delay constraints. The expense of distributing high frequency signals in a synchronous manner using conventional techniques is a barrier to building relatively large systems.
It would be desirable to implement a separate clock synchronous architecture.